The present invention relates to processor data/instruction flow and storage. More specifically, the present invention relates to a system and method for substituting specific dynamic pipelines with static queues in a pipelined processor.
The architecture of many processors in the art is based on a pipelined design. A processor pipeline is analogous to an assembly line, wherein the complete task is partitioned into a sequence of small sub-steps and each sub-step is carried out at a different stage of the pipeline. The pipelined design allows the processor to simultaneously process several instructions, with each pipeline stage processing successive instructions as they pass through that stage.
When a computational task is broken down into sub-steps to be executed in a pipelined fashion, often a partial result generated at a certain stage has to travel several stages down the pipeline unchanged before it is used by another stage downstream. This process is known as xe2x80x98stagingxe2x80x99.
FIG. 1 provides an illustration of a typical staging pipeline as known in the art. In this diagram, the data, comprising four input bits 100,101,102,103, is staged down a pipeline of 5 stages 111,112,113,114,115. The number of stages of a pipeline is referred to as the xe2x80x9cdepthxe2x80x9d (xe2x80x98dxe2x80x99) of the pipeline. The number of inputs is referred to as the xe2x80x9cwidthxe2x80x9d (xe2x80x98wxe2x80x99) of the pipeline.
Typical pipelined processors such as is shown in FIG. 1, although transporting data a relatively short distance, consume significant power. The power is consumed by the changes in state of each of the flip-flops 120, by the line segments 122 connecting each stage to its successor, and most significantly, by the clock grid 124.
Therefore, there is a need to improve upon the current system and method of staging pipelined processors in order to reduce power consumption and to simplify the process of clock tree design, in addition to other advantages.